As known, a level-shifter is a device configured to process a digital input signal having a swing comprised between the ground potential GND and a first supply voltage VDD1 to generate as output a corresponding digital signal having its swing comprised between the ground potential GND and a second supply voltage VDD2. Generally, such second supply voltage VDD2 is higher than the first supply voltage VDD1.
For example, the digital input signal of the level shifter may be a signal processed in a low-voltage portion of the circuit having its swing comprised between the ground potential GND and the first supply voltage VDD1=1.2V to reduce power dissipation. The output signal generated by the level shifter can drive a power buffer so that to commutate between the ground potential GND itself and the second supply voltage VDD2 corresponding to the battery voltage of a mobile phone, which is usually a time-varying voltage between 2.3V and 5V.
However, MOS transistors manufactured according to the most recent technologies, for example a 40 nm manufacturing process, would incur breakdowns or unacceptable degradations when used with voltages having a swing varying between the ground potential GND and the above mentioned battery voltage. In this case, known configurations of a level shifter from low voltage input swing to high voltage output swing cannot be used.
In order to overcome such inconvenience, particularly for driving an output P-channel MOS transistor, one solution is to use a level shifter configured to shift its input voltage having a swing comprised between the first supply voltage VDD1 and the ground potential GND to an output voltage having a swing from the second supply voltage VDD2 (corresponding to P-MOS switched-off) to VDD2−k (corresponding to P-MOS switched-on) which is suitable to drive the gate of the P-MOS. In this case, k indicates a voltage value that can be fixed so that to be compatible with reliability issues and acceptable overdrive. Values for k are, for example, comprised in the range 1.8V-2.2V.
To this end, a level shifter that can be employed is described in the article “A Class-AB/D Audio Power Amplifier for Mobile Applications Integrated into a 2.5G/3G Baseband Processor”, by Willem H. Groeneweg et al., IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: Regular Papers, vol. 57, No 5, May 2010. The structure of such level shifter is shown in FIG. 4 and indicated with the reference number 300.
Particularly, a first M3 and a second M4 N-MOS transistor of level shifter 300 have their gate terminals connected, respectively, to a first 301 and to a second 302 input of the level shifter 300. Such first input 301 is configured to receive a digital low-voltage input signal VA that can correspond to the ground potential GND or to the first supply voltage VDD1. The first input 301 of the level shifter 300 is connected to the second input 302 through an inverter 303, therefore the second input 302 of the level shifter 300 is configured to receive a first low-voltage input signal VM which is logically opposite to the low-voltage input signal VA. In more detail, such first low-voltage input signal VM corresponds to the ground potential GND or to the first supply voltage VDD1 when the low-voltage input signal VA corresponds to the first supply voltage VDD1 or to the ground potential GND, respectively. In this way, the first M3 and second M4 transistors are alternatively switched on or off on the basis of the value assumed by the input signal VA.
Moreover, the level shifter 300 comprises a current mirror including further N-MOS transistors M1 and M2 operating to mirror a first polarization current Ig in a second polarization current IM applied to the source terminals of the first M3 and second M4 N-MOS transistors.
On the basis of the input signal VA, the second polarization current IM can flow alternatively in a first branch and in a second branch of the level shifter 300. The first branch includes the first N-MOS transistor M3, a third N-MOS transistor M5, activated by a bias voltage VBIAS, and a first resistor R1 connected in series with them. The second branch includes the second N-MOS transistor M4, a fourth N-MOS transistor M6, activated by the same bias voltage VBIAS, and a second resistor R2 connected in series with them. Particularly, the first R1 and the second R2 resistor are connected between the second supply voltage VDD2 and, respectively, a first 304 and a second 305 output of the level shifter 300.
In view of the symmetrical structure of the known level shifter 300, the following conditions are valid for transistors and resistors: M3=M4, M5=M6, R1=R2.
In addition, the level shifter 300 comprises a first M7 and a second M8 P-MOS transistor where M7=M8. The first P-MOS transistor M7 is connected between the second supply voltage VDD2 and the first output 304 of the level shifter 300 and has its gate terminal connected to the second output 305 of the level shifter. The second P-MOS transistor M8 is connected between the second supply voltage VDD2 and the second output 305 and its gate terminal is connected to the first output 304 of the level shifter.
When the input signal VA corresponds to the first supply voltage VDD1, the second polarization current IM flows in the first branch of the level shifter 300 and generates over the first resistor R1 a voltage drop R1IM so that the voltage value on the first output 304 of the level shifter is VDD2−R1IM. The second supply voltage VDD2 is connected to the second output 305 by the second P-MOS transistor M8 being switched on.
When the input signal VA corresponds to the ground potential GND, the second polarization current IM flows in the second branch of the level shifter 300 and generates over the second resistor R2 a voltage drop R2IM so that the voltage value on the second output 305 of the level shifter is VDD2−R2IM. The second supply voltage VDD2 is connected to the first output 304 by the first P-MOS transistor M7 being switched on.
The level shifter 300 known in the art shows its limits when it is used to drive a large capacitive load CL, for example a capacitive load of 2 pF. FIG. 5 shows time diagrams of the input signal VA and of output signal Vo related to the level shifter 300 of FIG. 4. Time diagram related to the output signal Vo is obtained assuming the second polarization current IM=5 μA and R1=R2=360 kΩ. In fact, in this case the transition time of the output signal Vo generated by the level shifter 300 can reach a value, for example, of 1 μsec that is unacceptable for many applications.
It should be observed that, in the level shifter of FIG. 4, the fall time mainly depends on the values chosen for resistors R1=R2, on the capacitive load CL and on the second polarization current IM. The rise time mainly depends on the values of capacitive load CL and on the resistors R1=R2. For example, for a capacitive load CL=2 pF, to reduce both rise and fall times, the reduction of both resistors R1=R2 is required. In this case, in order to ensure that the low voltage value VDD2−R1IM=VDD2−k of the output signal Vo is maintained compatible with reliability issues and acceptable overdrive as indicated above, the second polarization current IM should be increased.
In other words, to reduce the transition time with the solution for a level shifter 300 known in the art, the power consumption should be increased. This is often unacceptable.